High bandwidth communication systems require high speed digital-to-analog conversion. Time-interleaving two digital-to-analog converters (DACs) is a technique that can help meet high bandwidth requirements. The two DACs may be referred to as DAC cores or sub-DACs. In a time-interleaved DAC, the two sub-DACs may be coupled in parallel and configured to operate alternately at a frequency FS. The clock signals applied to the two sub-DACs may be complementary. For example, the clock signal applied to one of the sub-DACs may be delayed with respect to the clock signal applied to the other sub-DAC by 180 degrees (i.e., 0.5/FS). Operating the two sub-DACs in this manner results in the interleaved DAC producing an analog output waveform having an effective sample rate of 2FS.
Time skew between the two sub-DACs degrades the image attenuation and the interleaving operation. Such time skew can be caused not only by phase imbalance or skew between the two clock signals but also by integrated circuit process variation between the two sub-DACs. It is desirable to reduce the phase imbalance or skew between the sub-DACs of a time-interleaved DAC and hence improve the image attenuation.